MC912D60AVPVE8 Datasheet, PDF (316/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers

MSCAN Controller
17.7 Protocol Violation Protection
The msCAN12 will protect the user from accidentally violating the CAN
protocol through programming errors. The protection logic implements
the following features:
• The receive and transmit error counters cannot be written or
otherwise manipulated.
• All registers which control the configuration of the msCAN12
cannot be modified while the msCAN12 is on-line. The SFTRES
bit in CMCR0 (see msCAN12 Module Control Register 0
(CMCR0)) serves as a lock to protect the following registers:
– msCAN12 module control register 1 (CMCR1)
– msCAN12 bus timing register 0 and 1 (CBTR0, CBTR1)
– msCAN12 identifier acceptance control register (CIDAC)
– msCAN12 identifier acceptance registers (CIDAR0–7)
– msCAN12 identifier mask registers (CIDMR0–7)
• The TxCAN pin is forced to recessive when the msCAN12 is in any
of the low power modes.
17.8 Low Power Modes
In addition to normal mode, the msCAN12 has three modes with
reduced power consumption: SLEEP, SOFT_RESET and
POWER_DOWN mode. In SLEEP and SOFT_RESET modes, power
consumption is reduced by stopping all clocks except those to access
the registers. In POWER_DOWN mode, all clocks are stopped and no
power is consumed.
The WAI and STOP instructions put the MCU in low power consumption
stand-by modes. Table 17-2 summarizes the combinations of msCAN12
and CPU modes. A particular combination of modes is entered for the
given settings of the bits CSWAI, SLPAK, and SFTRES. For all modes,
an msCAN wake-up interrupt can occur only if SLPAK=WUPIE=1. While
the CPU is in Wait Mode, the msCAN12 can be operated in Normal
Technical Data
316
MSCAN Controller
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor