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MC912D60AVPVE8 Datasheet, PDF (242/460 Pages) Freescale Semiconductor, Inc – HC12 Microcontrollers | |||
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Enhanced Capture Timer
TOF â Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation.)
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC0 â Timer Input Capture/Output Compare Register 0
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC1 â Timer Input Capture/Output Compare Register 1
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC2 â Timer Input Capture/Output Compare Register 2
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC3 â Timer Input Capture/Output Compare Register 3
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC4 â Timer Input Capture/Output Compare Register 4
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC5 â Timer Input Capture/Output Compare Register 5
1
Bit 0
9
Bit 8
1
Bit 0
$0090â$0091
1
Bit 0
9
Bit 8
1
Bit 0
$0092â$0093
1
Bit 0
9
Bit 8
1
Bit 0
$0094â$0095
1
Bit 0
9
Bit 8
1
Bit 0
$0096â$0097
1
Bit 0
9
Bit 8
1
Bit 0
$0098â$0099
1
Bit 0
9
Bit 8
1
Bit 0
$009Aâ$009B
Technical Data
242
Enhanced Capture Timer
MC68HC912D60A â Rev. 3.1
Freescale Semiconductor
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