I.MX27 Datasheet, PDF (90/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Electrical Characteristics
NOTE
All the timings for the SSI are given for a non-inverted serial clock polarity
(TSCKP/RSCKP = 0) and a non-inverted frame sync (TFSI/RFSI = 0). If the
polarity of the clock and/or the frame sync have been inverted, all the timing
remains valid by inverting the clock signal STCK/SRCK and/or the frame
sync STFS/SRFS shown in the tables and in the figures.
All timings are on AUDMUX pads when the SSI is being used for data
transfer.
“Tx” and “Rx” refer to the Transmit and Receive sections of the SSI.
For internal Frame Sync operation using external clock, the FS timing will
be same as that of Tx Data, for example, during the AC97 mode of
operation.
4.3.11.4 SSI Receiver Timing with External Clock
Figure 51 and Figure 52 show the SSI receiver timing with external clock, and Table 49 lists the timing
parameters.
SS23
SS22
SS26
SS25
SS24
AD1_TXC
(Input)
SS28
AD1_TXFS (bl)
(Input)
AD1_TXFS (wl)
(Input)
AD1_RXD
(Input)
SS30
SS32
SS35
SS40
SS41
SS36
Figure 51. SSI Receiver with External Clock Timing Diagram
SS34
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
90
Freescale Semiconductor