I.MX27 Datasheet, PDF (27/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Signal Descriptions
3 Signal Descriptions
This section discusses the following:
• Identifies and defines all device signals in text, tables, and (as appropriate) figures. Signals can be
organized by group, as applicable.
• Contains pin-assignment/contact-connection diagrams, if the sequence of information in the data
sheet requires them to be included here.
Table 3 shows the i.MX27/MX27L signal descriptions.
Table 3. i.MX27/MX27L Signal Descriptions
Pad Name
Function/Notes
A [13:0]
MA10
A [25:14]
SDBA[1:0]
SD[31:0]
SDQS[3:0]
DQM0–DQM3
EB0
EB1
OE
CS [5:0]
ECB
LBA
BCLK
RW
RAS
CAS
SDWE
SDCKE0
External Bus/Chip Select (EMI)
Address bus signals, shared with SDRAM/MDDR, WEIM and PCMCIA, A[10] for
SDRAM/MDDR is not the address but the pre-charge bank select signal.
Address bus signals for SDRAM/MDDR
Address bus signals, shared with WEIM and PCMCIA
SDRAM/MDDR bank address signals
Data bus signals for SDRAM, MDDR
MDDR data sample strobe signals
SDRAM data mask strobe signals
Active low external enable byte signal that controls D [15:8], shared with PCMCIA PC_REG.
Active low external enable byte signal that controls D [7:0], shared with PCMCIA PC_IORD.
Memory Output Enable—Active low output enables external data bus, shared with PCMCIA
PC_IOWR.
Chip Select—The chip select signals CS [3:2] are multiplexed with CSD [1:0] and are selected
by the Function Multiplexing Control Register (FMCR) in the System Control chapter. By default
CSD [1:0] is selected. DTACK is multiplexed with CS4.
CS[5:4] are multiplexed with ETMTRACECLK and ETMTRACESYNC; PF22, 21.
Active low input signal sent by flash device to the EIM whenever the flash device must terminate
an on-going burst sequence and initiate a new (long first access) burst sequence.
Active low signal sent by flash device causing external burst device to latch the starting burst
address.
Clock signal sent to external synchronous memories (such as burst flash) during burst mode.
RW signal—Indicates whether external access is a read (high) or write (low) cycle. This signal
is also shared with the PCMCIA PC_WE.
SDRAM/MDDR Row Address Select signal
SDRAM/MDDR Column Address Select signal
SDRAM Write Enable signal
SDRAM Clock Enable 0
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
Freescale Semiconductor
27