I.MX27 Datasheet, PDF (76/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Electrical Characteristics
Table 38. SDR SDRAM Write Timing Parameters (continued)
ID
Parameter
Symbol
Min
Max
Unit
SD13
SD14
Note:
Data setup time
Data hold time
tDS
2.0
—
ns
tDH
1.3
—
ns
1 _{SD11 and SD12 are determined by SDRAM controller register settings.}
NOTE
SDR SDRAM CLK parameters are being measured from the 50%
point—that is, high is defined as 50% of signal value and low is defined as
50% of signal value.
The timing parameters are similar to the ones used in SDRAM data
sheets—that is, Table 38 indicates SDRAM requirements. All output signals
are driven by the ESDCTL at the negative edge of SDCLK and the
parameters are measured at maximum memory frequency.
SDCLK
SDCLK
CS
SD1
SD2
SD3
RAS
CAS
WE
SD11
SD10
SD10
SD6
ADDR
BA
SD7
Figure 39. SDRAM Refresh Timing Diagram
ROW/BA
Table 39. SDRAM Refresh Timing Parameters
ID
Parameter
SD1 SDRAM clock high-level width
SD2 SDRAM clock low-level width
Symbol
tCH
tCL
Min
Max
Unit
3.4
4.1
ns
3.4
4.1
ns
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
76
Freescale Semiconductor