I.MX27 Datasheet, PDF (59/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Electrical Characteristics
4.3.2.3 MII Asynchronous Inputs Signal Timing (FEC_CRS and FEC_COL)
Figure 19 shows the MII asynchronous input timings, and Table 27 lists the timing parameters.
FEC_CRS, FEC_COL
M9
Figure 19. MII Asynchronous Inputs Signal Timing Diagram
Table 27. MII Asynchronous Inputs Signal Timing Parameter
ID
Parameter
M9¹
FEC_CRS to FEC_COL minimum pulse width
Note:
1 _{FEC_COL has the same timing in 10 Mbit 7-wire interface mode.}
Min
Max
Unit
1.5
—
FEC_TX_CLK period
4.3.2.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC)
The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. The MDC frequency should
be equal to or less than 2.5 MHz to be compliant with IEEE 802.3 MII specification. However the FEC
can function correctly with a maximum MDC frequency of 15 MHz.
Figure 20 shows the MII serial management channel timings, and Table 28 lists the timing parameters.
M14
M15
FEC_MDC (output)
M10
FEC_MDIO (output)
M11
FEC_MDIO (input)
M12 M13
Figure 20. MII Serial Management Channel Timing Diagram
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
Freescale Semiconductor
59