I.MX27 Datasheet, PDF (32/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Signal Descriptions
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Pad Name
Function/Notes
CSI_D1
CSI_D0
Sensor port data, multiplexed with UART6_RXD; PB11
Sensor port data, multiplexed with UART6_TXD; PB10
Serial Audio Port—SSI (Configurable to I2S Protocol and AC97) (2 to 4)
SSI1_CLK
SSI1_TXD
SSI1_RXD
SSI1_FS
SSI2_CLK
SSI2_TXD
SSI2_RXD
SSI2_FS
SSI3_CLK
SSI3_TXD
SSI3_RXD
SSI3_FS
SSI4_CLK
SSI4_TXD
SSI4_RXD
SSI4_FS
Serial clock signal that is output in master or input in slave; PC23
Transmit serial data; PC22
Receive serial data; PC21
Frame Sync signal that is output in master and input in slave; PC20
Serial clock signal that is output in master or input in slave, multiplexed with GPT4_TIN. PC27
Transmit serial data signal, multiplexed with GPT4_TOUT; PC26
Receive serial data, multiplexed with GPT5_TIN; PC25
Frame Sync signal which is output in master and input in slave, multiplexed with GPT5_TOUT:
PC24
Serial clock signal which is output in master or input in slave. This signal is multiplexed with
SLCDC2_CLK; through GPIO multiplexed with PC_WAIT_B; PC31.
Transmit serial data signal which is multiplexed with SLCDC2_CS, through GPIO multiplexed
with PC_READY; PC30
Receive serial data which is multiplexed with SLCDC2_RS; through GPIO multiplexed with
PC_VS1; PC29
Frame Sync signal which is output in master and input in slave. This signal is multiplexed with
SLCDC2_D0; through GPIO multiplexed with PC_VS1; PC28.
Serial clock signal which is output in master or input in slave; through GPIO multiplexed with
PC_BVD1; PC19
Transmit serial data; through GPIO multiplexed with PC_BVD2; PC18
Receive serial data; through GPIO multiplexed with IOIS16; PC17
Frame Sync signal which is output in master and input in slave; PC16
General Purpose Timers (X6)
TIN
Timer Input Capture or Timer Input Clock—The signal on this input is applied to GPT 1–3
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL,
Clock, and Reset Controller module, and is also multiplexed with GPT6_TOUT; PC15.
TOUT1
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with
SSI1_MCLK and SSI2_MCLK signal of SSI1 and SSI2. The pin name of this signal is simply
TOUT, and is also multiplexed with GPT6_TIN; PC14.
Note: TOUT2, TOUT3 are multiplexed with PWMO pad; GPT4 and GPT5 signals are multiplexed with SSI2 pads.
USB2.0
USBOTG_DIR/TXDM
USBOTG_STP/TXDM
USB OTG direction/Transmit Data Minus signal, multiplexed with KP_ROW7A; PE2
USB OTG Stop signal/Transmit Data Minus signal, multiplexed with KP_ROW6A; PE1
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
32
Freescale Semiconductor