I.MX27 Datasheet, PDF (4/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Functional Description and Application Information
1.3 Ordering Information
Table 1 provides ordering information for the MAPBGA, lead-free packages.
Table 1. Ordering Information¹
Device
Temperature
Package
MCIMX27VOP4A!
–20° C to +85° C
1816-01
MCIMX27LVOP4A!
–20° C to +85° C
1816-01
MCIMX27MOP4A!
–40° C to +85° C
1931-04
MCIMX27LMOP4A!
–40° C to +85° C
1931-04
MCIMX27VJP4A
–20° C to +85° C
1816-01
MCIMX27LVJP4A
–20° C to +85° C
1816-01
MCIMX27MJP4A
–40° C to +85° C
1931-04
MCIMX27LMJP4A
–40° C to +85° C
1931-04
1 _{Because of an order from the United States International Trade Commission, BGA-packaged}
product lines and part numbers indicated here currently are not available from Freescale for
import or sale in the United States prior to September 2010: Indicated by the Icon (!)
2 Functional Description and Application Information
2.1 ARM926 Microprocessor Core Platform
The ARM926 Platform consists of the ARM926EJ-S processor, ETM9, ETB9, a 6 × 3 Multi-Layer AHB
crossbar switch (MAX), and a “primary AHB” complex.
• The instruction bus (I-AHB) of the ARM926EJ-S processor is connected directly to MAX Master
Port 0.
• The data bus (D-AHB) of the ARM926EJ-S processor is connected directly to MAX Master Port 1.
Four alternate bus master interfaces are connected to MAX Master Ports 2–5. Three slave ports of the
MAX are AHB-Lite compliant buses. Slave Port 0 is designated as the “primary” AHB. The primary AHB
is internal to the platform and has five slaves connected to it: the AITC interrupt module, the MCTL
memory controller, and two AIPI peripheral interface gaskets. Slave Ports 1 and 2 of the MAX are referred
to as “secondary” AHBs. Each of the secondary AHB interfaces is only accessible off platform.
The ARM926EJ-S processor supports the 32-bit and 16-bit ARM Thumb instruction sets, enabling the
user to trade off between high performance and high-code density. The ARM926EJ-S processor includes
features for efficient execution of Java byte codes, providing Java performance similar to the just-in-time
(JIT) compiler—which is a type of Java compiler—but without the associated code overhead.
The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both
hardware and software debugging. The ARM926EJ-S processor has a Harvard cached architecture and
provides a complete high-performance processor subsystem, including the following:
• An ARM9EJ-S integer core
• A Memory Management Unit (MMU)
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
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