I.MX27 Datasheet, PDF (55/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Electrical Characteristics
Table 23. CSPI Interface Timing Parameters
ID
Num
Parameter Description
Symbol
Minimum
Maximum
t1
CSPI master SCLK cycle time
t_clko
t2
CSPI master SCLK high time
t_clkoH
t3
CSPI master SCLK low time
t_clkoL
t1’
CSPI slave SCLK cycle time
t_clki
t2’
CSPI slave SCLK high time
t_clkiH
t3’
CSPI slave SCLK low time
t_clkiL
t4
CSPI SCLK transition time
t_pr1
t5
SSn output pulse width
t_Wsso
t5’
SSn input pulse width
t_Wssi
t6
SSn output asserted to first SCLK edge (SS output t_Ssso
setup time)
t6’
SSn input asserted to first SCLK edge (SS input
t_Sssi
setup time)
t7
CSPI master: Last SCLK edge to SSn deasserted t_Hsso
(SS output hold time)
t7’
CSPI slave: Last SCLK edge to SSn deasserted
t_Hssi
(SS input hold time)
t8
CSPI master: CSPI1_RDY low to SSn asserted
t_Srdy
(CSPI1_RDY setup time)
t9
CSPI master: SSn deasserted to CSPI1_RDY low
t_Hrdy
t10 Output data setup time
t_Sdatao
t11 Output data hold time
t_Hdatao
t12 Input data setup time
t_Sdatai
t13 Input data hold time
t_Hdatai
Note:
1 _{The output SCLK transition time is tested with 25 pF drive.}
2 _{Tsclk = CSPI clock period}
3 _{Twait = Wait time as per the Sample Period Control Register value.}
4 _{Tper = CSPI reference baud rate clock period (PERCLK2)}
5 _{Tipg = CSPI main clock IPG_CLOCK period}
45.12
22.65
22.47
60.2
30.1
30.1
2.6
2T_sclk2
+T
3
wait
T_per4
3T_sclk
T_per + 20 ns
2T_sclk
30
2T_per
0
(t_clkoL or t_clkoH or
t_clkiL or t_clkiH) -
T_ipg5
t_clkoL or t_clkoH or
t_clkiL or t_clkiH
T_ipg + 0.5
5
-
—
—
—
—
—
8.5
—
—
—
—
—
—
5T_per
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
—
—
—
—
—
ns
—
ns
—
—
ns
ns
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
Freescale Semiconductor
55