I.MX27 Datasheet, PDF (34/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Signal Descriptions
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Pad Name
Function/Notes
VSYNC
Frame Sync or Vsync—This signal also serves as the clock signal output for gate;
driver (dedicated signal SPS for Sharp panel HR-TFT); PA29.
HSYNC
Line Pulse or HSync; PA28
SPL_SPR
Sampling start signal for left and right scanning. Through GPIO, this signal is multiplexed with
the SLCDC1_CLK; PA27.
PS
Control signal output for source driver (Sharp panel dedicated signal). This signal is multiplexed
with the SLCDC1_CS; PA26.
CLS
Start signal output for gate driver. This signal is invert version of PS (Sharp panel dedicated
signal). This signal is multiplexed with the SLCDC1_RS; PA25.
REV
Signal for common electrode driving signal preparation (Sharp panel dedicated signal). This
signal is multiplexed with SLCDC1_D0; PA24.
LD [17:0]
LCD Data Bus—All LCD signals are driven low after reset and when LCD is off. Through GPIO,
LD[15:0] signals are multiplexed with SLCDC1_DAT[15:0], SLCDC. PA23–PA6.
LSCLK
Shift Clock; PA5
Note: SLCDC signals are multiplexed with LCDC signals.
ATA (not available on i.MX27L)
ATA_DATA15–0
ATA Data Bus, [15:0] are multiplexed with
ETMTRACEPKT4–12,
FEC_MDIO,
ETMTRACEPKT13–14
SD3_D3–0;
Through GPIO also are multiplexed with SLCDC 15–0, and FEC signals; PF23, PD16–PD2.
Noisy I/O Supply Pins
N_VDD1–15, A_VDD
Noisy Supply for the I/O pins. There are 16 I/O voltage pads, N_VDD1 through N_VDD15 + A_VDD.
Analog Supply Pins
FPM_VDD
MPLL_VDD
OSC26_VDD
UPLL_VDD
OSC32_VDD
OSC32VSS
FPMVSS
MPLLVSS
OSC26VSS
UPLLVSS
Supply for analog blocks
Quiet GND for analog blocks
Q_VDD
QVSS
Q_VDD Internal Power Supply
Power supply pins for silicon internal circuitry
GND pins for silicon internal circuitry
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
34
Freescale Semiconductor