I.MX27 Datasheet, PDF (73/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Electrical Characteristics
4.3.9 SDRAM (DDR and SDR) Memory Controller
Figure 37, Figure 38, Figure 39, Figure 40, Figure 41, and Figure 42 depict the timings pertaining to the
ESDCTL module, which interfaces Mobile DDR or SDR SDRAM. Table 37, Table 38, Table 39, Table 40,
Table 41, and Table 42 list the timing parameters.
SDCLK
SDCLK
CS
SD1
SD2
SD4
SD3
SD5
SD4
RAS
CAS
SD5
SD4
SD4
WE
SD5
SD5
SD6
ADDR
ROW/BA
SD7
COL/BA
SD10
DQ
SD8
SD9
Data
SD4
DQM
Note: CKE is high during the read/write cycle.
SD5
Figure 37. SDRAM Read Cycle Timing Diagram
Table 37. DDR/SDR SDRAM Read Cycle Timing Parameters
ID
Parameter
SD1
SDRAM clock high-level width
SD2
SDRAM clock low-level width
SD3
SDRAM clock cycle time
SD4
CS, RAS, CAS, WE, DQM, CKE setup time
SD5
CS, RAS, CAS, WE, DQM, CKE hold time
Symbol
Min
Max
Unit
tCH
tCL
tCK
tCMS
tCMH
3.4
4.1
ns
3.4
4.1
ns
7.5
—
ns
2.0
—
ns
1.8
—
ns
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
Freescale Semiconductor
73