I.MX27 Datasheet, PDF (24/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Functional Description and Application Information
• Bypass mode to route Host Port 1 signals to OTG I/O port
• High Speed /Full Speed/Low Speed Host Only core (Host 2)
• Full Speed/Low Speed interface for Serial transceiver
• TLL function for direct connection to USB peripheral in FS/LS (serial) operation
• High-speed OTG core
The USB module has two main modes of operation: Normal mode and Bypass mode. Furthermore, the
USB interfaces can be configured for high-speed operation (480 Mbps) and/or full/low speed operation
(12/1.5 Mbps). In Normal mode, each USB core controls its corresponding port. In additional to th4e
major operational modes, each port can work in one or more modes, as follows:
PHY mode
In PHY mode, an external serial transceiver is connected to the port. This is used
for off-board USB connections.
TLL mode
In TLL mode, internal logic is enabled to emulate the functionality of two
back-to-back connected transceivers. This mode is typically used for on-board
USB connections to USB-capable peripherals.
Host Port 2 supports ULPI and Serial Transceivers. The OTG port requires a transceiver and is intended
for off-board USB connections.
Serial Interface mode
In serial mode, a serial OTG transceiver must be connected. The port does not
support dedicated signals for OTG signaling. Instead, a transceiver with built-in
OTG registers must be used. Typically, the Transceiver registers are accessible
over an I2C or SPI interface.
ULPI mode
In this mode, a ULPI transceiver is connected to the port pins to support
high-speed off board USB connection.
Bypass mode
Low Power mode
Bypass mode affects the operation of the OTG port and Host Port 1. This mode is
only available when a serial transceiver is used on the OTG port, and the
peripheral device on Port 1 is using a TLL connection. Bypass mode is activated
by setting the bypass bit in the USBCONTROL register. In this mode, the USB
OTG port connections are internally routed to the USB Host 1 port, such that the
transceiver on the OTG port connects to a peripheral USB device on Host Port 1.
The OTG core and the Host 1 core are disconnected from their ports when bypass
is active.
Each of the three USB cores has an associated power control module that is
controlled by the USB core and clocked on a 32-kHz clock. When a USB bus is
idle, the transceiver can be placed in low-power mode (suspend), after which the
clocks to the USB core can be stopped. The 32-kHz low power clock must remain
active as it is needed for walk-up detection.
2.3.37 Watchdog Timer Module (WDOG)
The Watchdog Timer module (WDOG) protects against system failures by providing a method of escaping
from unexpected events or programming errors. Once the WDOG module is activated, it must be serviced
by software on a periodic basis. If servicing does not take place, the timer times out. Upon a time-out, the
WDOG Timer module either asserts the wdog signal or a system reset signal wdog_rst, depending on
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
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Freescale Semiconductor