I.MX27 Datasheet, PDF (28/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Signal Descriptions
Pad Name
SDCKE1
SDCLK
SDCLK_B
NFWE_B
NFRE_B
NFALE
NFCLE
NFWP_B
NFCE_B
NFRB
D[15:0]
PC_CD1_B
PC_CD2_B
PC_WAIT_B
PC_READY
PC_PWRON
PC_VS1
PC_VS2
PC_BVD1
PC_BVD2
PC_RST
IOIS16
PC_RW_B
PC_POE
CLKO
EXT_60M
EXT_266M
OSC26M_TEST
RESET_IN
28
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Function/Notes
SDRAM Clock Enable 1
SDRAM Clock
SDRAM Clock_B
NFC Write enable signal, multiplexed with ETMPIPESTAT2; PF6
NFC Read enable signal, multiplexed with ETMPIPESTAT1; PF5
NFC Address latch signal, multiplexed with ETMPIPESTAT0; PF4
NFC Command latch signal, multiplexed with ETMTRACEPKT0; PF1
NFC Write Permit signal, multiplexed with ETMTRACEPKT1; PF2
NFC Chip enable signal, multiplexed with ETMTRACEPKT2; PF3
NFC read Busy signal, multiplexed with ETMTRACEPKT3; PF0
Data Bus signal, shared with EMI, PCMCIA, and NFC
PCMCIA card detect signal, multiplexed with ATA ATA_DIOR signal; PF20
PCMCIA card detect signal, multiplexed with ATA ATA_DIOW signal; PF19
PCMCIA WAIT signal, multiplexed with ATA ATA_CS1 signal; PF18
PCMCIA READY/IRQ signal, multiplexed with ATA ATA_CS0 signal; PF17
PCMCIA signal, multiplexed with ATA ATA_DA2 signal; PF16
PCMCIA voltage sense signal, multiplexed with ATA ATA_DA1 signal; PF14
PCMCIA voltage sense signal, multiplexed with ATA ATA_DA0 signal; PF13
PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMARQ signal; PF12
PCMCIA Battery voltage detect signal, multiplexed with ATA ATA_DMACK signalPF11
PCMCIA card reset signal, multiplexed with ATA ATA_RESET_B signal; PF10
PCMCIA mode signal, multiplexed with ATA ATA_INTRQ signal; PF9
PCMCIA read write signal, multiplexed with ATA ATA_IORDY signal; PF8
PCMCIA output enable signal, multiplexed with ATA ATA_BUFFER_EN signal; PF7
Clocks and Resets
Clock Out signal selected from internal clock signals. Refer to the clock controller for internal
clock selection; PF15.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
This is a special factory test signal. To ensure proper operation, leave this signal as a no
connect.
Master Reset—External active low Schmitt trigger input signal. When this signal goes active,
all modules (except the reset module, SDRAMC module, and the clock control module) are
reset.
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
Freescale Semiconductor