I.MX27 Datasheet, PDF (57/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Electrical Characteristics
Table 24. DMAC Timing Parameters
Parameter
Description
3.0 V
WCS
BCS
1.8 V
WCS
BCS
Unit
Tmin_assert
Minimum assertion time of External Grant signal 8hclk+8.6 8hclk+2.74 8hclk+7.17 8hclk+3.25 ns
Tmax_req_assert Maximum External Request assertion time after 9hclk–20.66 9hclk–6.7 9hclk–17.96 9hclk–8.16 ns
assertion of Grant signal
Tmax_read
Maximum External Request assertion time after 8hclk–6.21 8hclk–0.77 8hclk–5.84 8hclk–0.66 ns
first read completion
Tmax_write
Maximum External Request assertion time after 3hclk–5.87 3hclk–8.83 3hclk–15.9 3hclkv91.2 ns
first write completion
4.3.2 Fast Ethernet Controller (FEC)
This section describes the AC timing specifications of the FEC. The MII signals are compatible with
transceivers operating at a voltage of 3.3 V.
4.3.2.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER,
and FEC_RX_CLK)
The receiver functions correctly up to a FEC_RX_CLK maximum frequency of 25 MHz + 1%. There is
no minimum frequency requirement. In addition, the FEC IPG clock frequency must exceed twice the
FEC_RX_CLK frequency.
Figure 17 shows the MII receive signal timings, and Table 25 lists the timing parameters.
M3
FEC_RX_CLK (input)
FEC_RXD[3:0] (inputs)
FEC_RX_DV
FEC_RX_ER
M4
M1
M2
Figure 17. MII Receive Signal Timing Diagram
ID
M1
M2
M3
Table 25. MII Receive Signal Timing Parameters
Parameter¹
Min Max
FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER to FEC_RX_CLK setup 5
FEC_RX_CLK to FEC_RXD[3:0], FEC_RX_DV, FEC_RX_ER hold 5
FEC_RX_CLK pulse width high
35%
—
—
65%
Unit
ns
ns
FEC_RX_CLK period
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
Freescale Semiconductor
57