I.MX27 Datasheet, PDF (29/148 Pages) Freescale Semiconductor, Inc – Multimedia Applications Processor

Pad Name
RESET_OUT
POR
XTAL26M
EXTAL26M
CLKMODE[1:0]
EXTAL32K
XTAL32K
Power_cut
Power_on_reset
osc32K_bypass
BOOT [3:0]
JTAG_CTRL
TRST
TDO
TDI
TCK
TMS
RTCK
SD1_CMD
SD1_CLK
Signal Descriptions
Table 3. i.MX27/MX27L Signal Descriptions (continued)
Function/Notes
Reset_Out—Output from the internal Hreset_b; and the Hreset can be caused by all reset
source: power on reset, system reset (RESET_IN), and watchdog reset.
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated
by an external RC circuit designed to detect a power-up event.
Oscillator output to external crystal
Crystal input (26 MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when internal
oscillator circuit is shut down.
These are special factory test signals. To ensure proper operation, do not connect to these
signals.
32 kHz crystal input (Note: in the RTC power domain)
Oscillator output to 32 kHz crystal (Note: in the RTC power domain)
(Note: in the RTC power domain)
(Note: in the RTC power domain)
The signal for osc32k input bypass (Note: in the RTC power domain)
Bootstrap
System Boot Mode Select—The operational system boot mode of the i.MX27/MX27L processor
upon system reset is determined by the settings of these pins. BOOT[1:0] are also used as
handshake signals to PMIC(VSTBY).
JTAG
JTAG Controller select signal—JTAG_CTRL is sampled during rising edge of TRST. Must be
pulled to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal
test purposes only.
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence JTAG test controller’s state machine. Sampled on rising edge of
TCK.
JTAG Return Clock used to enhance stability of JTAG debug interface devices. This signal is
multiplexed with 1-Wire; thus, utilizing 1-Wire will render RTCK unusable and vice versa; PE16.
Secure Digital Interface (X2)
SD Command bidirectional signal—If the system designer does not want to make use of the
internal pull-up, via the Pull-up enable register, a 4. 7K–69 K external pull up resistor must be
added. This signal is multiplexed with CSPI3_MOSI; PE22.
SD Output Clock. This signal is multiplexed with CSPI3_SCLK; PE23.
i.MX27 and i.MX27L Data Sheet, Rev. 1.5
Freescale Semiconductor
29