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S9S12G128F0MLH Datasheet, PDF (889/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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48 KByte Flash Module (S12FTMRG48K1V1)
26.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Offset Module Base + 0x0001
7
6
5
4
3
2
R
KEYEN[1:0]
RNV[5:2]
W
Reset
F1
F1
F1
F1
F1
F1
= Unimplemented or Reserved
Figure 26-6. Flash Security Register (FSEC)
1 Loaded from IFR Flash conï¬guration ï¬eld, during reset sequence.
1
0
SEC[1:0]
F1
F1
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash conï¬guration ï¬eld at global address 0x3_FF0F located in P-Flash memory (see Table 26-4) as
indicated by reset condition F in Figure 26-6. If a double bit fault is detected while reading the P-Flash
phrase containing the Flash security byte during the reset sequence, all bits in the FSEC register will be set
to leave the Flash module in a secured state with backdoor key access disabled.
Table 26-9. FSEC Field Descriptions
Field
Description
7â6
Backdoor Key Security Enable Bits â The KEYEN[1:0] bits deï¬ne the enabling of backdoor key access to the
KEYEN[1:0] Flash module as shown in Table 26-10.
5â2
Reserved Nonvolatile Bits â The RNV bits should remain in the erased state for future enhancements.
RNV[5:2]
1â0
Flash Security Bits â The SEC[1:0] bits deï¬ne the security state of the MCU as shown in Table 26-11. If the
SEC[1:0] Flash module is unsecured using backdoor key access, the SEC bits are forced to 10.
Table 26-10. Flash KEYEN States
KEYEN[1:0]
Status of Backdoor Key Access
00
DISABLED
01
DISABLED1
10
ENABLED
11
DISABLED
1 Preferred KEYEN state to disable backdoor key access.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
891
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