S9S12G128F0MLH Datasheet, PDF (53/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC

Device Overview MC9S12G-Family
1.7.1 Pin Assignment Overview
Table 1-6 provides a summary of which ports are available for each package option.
Port
Port AD/ADC Channels
Port A pins
Port B pins
Port C pins
Port D pins
Port E pins
Port J
Port M
Port P
Port S
Port T
Sum of Ports
I/O Power Pairs VDDX/VSSX
Table 1-6. Port Availability by Package Option
20 TSSOP
6
0
0
0
0
2
0
0
0
4
2
14
1/1
32 LQFP
8
0
0
0
0
2
0
2
4
6
4
26
1/1
48 LQFP
48 QFN
12
0
0
0
0
2
4
2
6
8
6
40
1/1
64 LQFP
16
0
0
0
0
2
8
4
8
8
8
54
1/1
100 LQFP
16
8
8
8
8
2
8
4
8
8
8
86
3/3
KGD (Die)
16
8
8
8
8
2
8
4
8
8
8
86
3/3
NOTE
To avoid current drawn from floating inputs, the input buffers of all
non-bonded pins are disabled.
1.7.2 Detailed Signal Descriptions
This section describes the signal properties. The relation between signals and package pins is described in
section 1.8 Device Pinouts.
1.7.2.1 RESET — External Reset Signal
The RESET signal is an active low bidirectional control signal. It acts as an input to initialize the MCU to
a known start-up state, and an output when an internal MCU function causes a reset. The RESET pin has
an internal pull-up device.
1.7.2.2 TEST — Test Pin
This input only pin is reserved for factory test. This pin has an internal pull-down device.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
55