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S9S12G128F0MLH Datasheet, PDF (764/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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Timer Module (TIM16B8CV3)
NOTE
The newly selected prescale factor will not take effect until the next
synchronized edge where all prescale counter stages equal zero.
23.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
Module Base + 0x000E
7
R
C7F
W
6
C6F
5
C5F
4
C4F
3
C3F
2
C2F
1
C1F
0
C0F
Reset
0
0
0
0
0
0
0
0
Figure 23-20. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write: Used in the clearing mechanism (set bits cause corresponding bits to be cleared). Writing a zero
will not affect current status of the bit.
Table 23-16. TRLG1 Field Descriptions
Note: Writing to unavailable bits has no effect. Reading from unavailable bits return a zero.
Field
7:0
C[7:0]F
Description
Input Capture/Output Compare Channel âxâ Flag â These flags are set when an input capture or output
compare event occurs. Clearing requires writing a one to the corresponding ï¬ag bit while TEN or PAEN is set to
one.
Note: When TFFCA bit in TSCR register is set, a read from an input capture or a write into an output compare
channel (0x0010â0x001F) will cause the corresponding channel ï¬ag CxF to be cleared.
23.3.2.13 Main Timer Interrupt Flag 2 (TFLG2)
Module Base + 0x000F
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
TOF
W
Reset
0
0
0
0
0
0
0
0
Unimplemented or Reserved
Figure 23-21. Main Timer Interrupt Flag 2 (TFLG2)
TFLG2 indicates when interrupt conditions have occurred. To clear a bit in the ï¬ag register, write the bit
to one while TEN bit of TSCR1 or PAEN bit of PACTL is set to one.
Read: Anytime
Write: Used in clearing mechanism (set bits cause corresponding bits to be cleared).
MC9S12G Family Reference Manual, Rev.1.23
766
Freescale Semiconductor
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