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S9S12G128F0MLH Datasheet, PDF (245/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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Port Integration Module (S12GPIMV1)
Table 2-88. PIE1AD Register Field Descriptions
Field
Description
7-0 Port AD interrupt enableâ
PIE1AD This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt ï¬ag masked)
2.4.3.63 Port AD Interrupt Flag Register (PIF0AD)
Address 0x027E (G1, G2)
7
R
PIF0AD7
W
Reset
0
Address 0x027E (G3)
6
PIF0AD6
0
5
PIF0AD5
0
4
PIF0AD4
0
3
PIF0AD3
0
2
PIF0AD2
0
7
6
5
4
3
2
R
0
0
0
0
PIF0AD3 PIF0AD2
W
Reset
0
0
0
0
0
0
Figure 2-62. Port AD Interrupt Flag Register (PIF0AD)
1 Read: Anytime
Write: Anytime, write 1 to clear
Access: User read/write1
1
0
PIF0AD1 PIF0AD0
0
0
Access: User read/write1
1
0
PIF0AD1 PIF0AD0
0
0
Table 2-89. PIF0AD Register Field Descriptions
Field
Description
7-0
PIF0AD
Port AD interrupt ï¬agâ
This ï¬ag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, âPin Interrupts and
Wakeupâ). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will
occur if the associated interrupt enable bit is set.
Writing a logic â1â to the corresponding bit ï¬eld clears the ï¬ag.
1 Active edge on the associated bit has occurred
0 No active edge occurred
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
247
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