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S9S12G128F0MLH Datasheet, PDF (155/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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Chapter 2
Port Integration Module (S12GPIMV1)
Revision History
Rev. No.
(Item No.)
V01.01
V01.02
V01.03
Date
(Submitted By)
01 Dec 2010
30 Aug 2011
15 Mar 2012
Sections
Affected
Substantial Change(s)
Table 2-4
Table 2-5
Table 2-8
Table 2-16
Table 2-17
⢠Removed TXD2 and RXD2 from PM1 and PM0 for G64
⢠Simpliï¬ed input buffer control description on port C and AD
⢠Corrected DAC signal priorities on pins PAD10 and PAD11 with shared
AMP and DACU output functions
2.4.3.40/2-23
2
2.4.3.48/2-23
8
2.4.3.63/2-24
7
2.4.3.64/2-24
8
⢠Corrected PIFx descriptions
Table 2-2./2-1
58
Table 2-4./2-1
62
⢠Added GA and GNA derivatives
2.1 Introduction
This section describes the S12G-family port integration module (PIM) in its conï¬gurations depending on
the family devices in their available package options.
It is split up into two parts, ï¬rstly determining the routing of the various signals to the available package
pins (âPIM Routingâ) and secondly describing the general-purpose port related logic (âPIM Portsâ).
2.1.1 Glossary
Table 2-1. Glossary Of Terms
Term
Pin
Signal
Deï¬nition
Package terminal with a unique number deï¬ned in the device pinout section
Input or output line of a peripheral module or general-purpose I/O function arbitrating
for a dedicated pin
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
157
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