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S9S12G128F0MLH Datasheet, PDF (1204/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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Electrical Characteristics
Table A-12. CPMU Conï¬guration for Pseudo Stop Current Measurement
CPMU REGISTER
CPMURTI
CPMUCOP
Bit settings/Conditions
RTDEC=0, RTR[6:4]=111, RTR[3:0]=1111;
WCOP=1, CR[2:0]=111
Table A-13. CPMU Conï¬guration for Run/Wait and Full Stop Current Measurement
CPMU REGISTER
Bit settings/Conditions
CPMUSYNR
VCOFRQ[1:0]=01,SYNDIV[5:0] = 24
CPMUPOSTDIV POSTDIV[4:0]=0
CPMUCLKS
PLLSEL=1
CPMUOSC
OSCE=0,
Reference clock for PLL is fref=firc1m trimmed to 1MHz
API settings for STOP current measurement
CPMUAPICTL APIEA=0, APIFE=1, APIE=0
CPMUAPITR
trimmed to 10Khz
CPMUAPIRH/RL set to $FFFF
1206
Table A-14. Peripheral Conï¬gurations for Run & Wait Current Measurement
Peripheral
MSCAN
SPI
SCI
PWM
ADC
DBG
Configuration
Conï¬gured to loop-back mode using a bit rate of 1Mbit/s
Conï¬gured to master mode, continuously transmit data
(0x55 or 0xAA) at 1Mbit/s
Conï¬gured into loop mode, continuously transmit data
(0x55) at speed of 57600 baud
Conï¬gured to toggle its pins at the rate of 40kHz
The peripheral is conï¬gured to operate at its maximum
speciï¬ed frequency and to continuously convert voltages on
all input channels in sequence.
The module is enabled and the comparators are conï¬gured
to trigger in outside range.The range covers all the code
executed by the core.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
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