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S9S12G128F0MLH Datasheet, PDF (748/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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Timer Module (TIM16B6CV3)
Setting OCPDx to zero allows the internal register to drive the programmed state to OCx. This allows a
glitch free switch over of port from general purpose I/O to timer output once the OCPDx bit is set to zero.
22.5 Resets
The reset state of each individual bit is listed within Section 22.3, âMemory Map and Register Deï¬nitionâ
which details the registers and their bit ï¬elds
22.6 Interrupts
This section describes interrupts originated by the TIM16B6CV3 block. Table 22-18 lists the interrupts
generated by the TIM16B6CV3 to communicate with the MCU.
Table 22-18. TIM16B6CV3 Interrupts
Interrupt
Offset Vector Priority
Source
Description
C[5:0]F
â
â
â
Timer Channel 5â0
Active high timer channel interrupts 5â0
TOF
â
â
â
Timer Overï¬ow
Timer Overï¬ow interrupt
The TIM16B6CV3 could use up to 7 interrupt vectors. The interrupt vector offsets and interrupt numbers
are chip dependent.
22.6.1 Channel [5:0] Interrupt (C[5:0]F)
This active high outputs will be asserted by the module to request a timer channel 7 â 0 interrupt. The TIM
block only generates the interrupt and does not service it. Only bits related to implemented channels are
valid.
22.6.2 Timer Overï¬ow Interrupt (TOF)
This active high output will be asserted by the module to request a timer overï¬ow interrupt. The TIM block
only generates the interrupt and does not service it.
MC9S12G Family Reference Manual, Rev.1.23
750
Freescale Semiconductor
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