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S9S12G128F0MLH Datasheet, PDF (231/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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Port Integration Module (S12GPIMV1)
1 Read: Anytime
Write: Anytime, write 1 to clear
Field
7-0
PIFP
Table 2-67. PIFP Register Field Descriptions
Description
Port P interrupt ï¬agâ
This ï¬ag asserts after a valid active edge was detected on the related pin (see Section 2.5.4.2, âPin Interrupts and
Wakeupâ). This can be a rising or a falling edge based on the state of the polarity select register. An interrupt will
occur if the associated interrupt enable bit is set.
Writing a logic â1â to the corresponding bit ï¬eld clears the ï¬ag.
1 Active edge on the associated bit has occurred
0 No active edge occurred
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
233
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