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S9S12G128F0MLH Datasheet, PDF (478/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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Analog-to-Digital Converter (ADC10B12CV2)
13.3.2.4 ATD Control Register 3 (ATDCTL3)
Writes to this register will abort current conversion sequence.
Module Base + 0x0003
R
W
Reset
7
DJM
0
6
S8C
5
S4C
4
S2C
3
S1C
2
FIFO
0
1
0
0
0
= Unimplemented or Reserved
Figure 13-6. ATD Control Register 3 (ATDCTL3)
Read: Anytime
Write: Anytime
Table 13-8. ATDCTL3 Field Descriptions
1
FRZ1
0
0
FRZ0
0
Field
Description
7
DJM
Result Register Data Justiï¬cation â Result data format is always unsigned. This bit controls justiï¬cation of
conversion data in the result registers.
0 Left justiï¬ed data in the result registers.
1 Right justiï¬ed data in the result registers.
Table 13-9 gives example ATD results for an input signal range between 0 and 5.12 Volts.
6â3
Conversion Sequence Length â These bits control the number of conversions per sequence. Table 13-10
S8C, S4C, shows all combinations. At reset, S4C is set to 1 (sequence length is 4). This is to maintain software continuity
S2C, S1C to HC12 family.
2
FIFO
Result Register FIFO Mode â If this bit is zero (non-FIFO mode), the A/D conversion results map into the result
registers based on the conversion sequence; the result of the ï¬rst conversion appears in the ï¬rst result register
(ATDDR0), the second result in the second result register (ATDDR1), and so on.
If this bit is one (FIFO mode) the conversion counter is not reset at the beginning or end of a conversion
sequence; sequential conversion results are placed in consecutive result registers. In a continuously scanning
conversion sequence, the result register counter will wrap around when it reaches the end of the result register
ï¬le. The conversion counter value (CC3-0 in ATDSTAT0) can be used to determine where in the result register
ï¬le, the current conversion result will be placed.
Aborting a conversion or starting a new conversion clears the conversion counter even if FIFO=1. So the ï¬rst
result of a new conversion sequence, started by writing to ATDCTL5, will always be place in the ï¬rst result register
(ATDDDR0). Intended usage of FIFO mode is continuos conversion (SCAN=1) or triggered conversion
(ETRIG=1).
Which result registers hold valid data can be tracked using the conversion complete ï¬ags. Fast ï¬ag clear mode
may be useful in a particular application to track valid data.
If this bit is one, automatic compare of result registers is always disabled, that is ADC10B12C will behave as if
ACMPIE and all CPME[n] were zero.
0 Conversion results are placed in the corresponding result register up to the selected sequence length.
1 Conversion results are placed in consecutive result registers (wrap around at end).
1â0
FRZ[1:0]
Background Debug Freeze Enable â When debugging an application, it is useful in many cases to have the
ATD pause when a breakpoint (Freeze Mode) is encountered. These 2 bits determine how the ATD will respond
to a breakpoint as shown in Table 13-11. Leakage onto the storage node and comparator reference capacitors
may compromise the accuracy of an immediately frozen conversion depending on the length of the freeze period.
MC9S12G Family Reference Manual, Rev.1.23
480
Freescale Semiconductor
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