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S9S12G128F0MLH Datasheet, PDF (184/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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Port Integration Module (S12GPIMV1)
2.4 PIM Ports - Memory Map and Register Deï¬nition
This section provides a detailed description of all PIM registers.
2.4.1 Memory Map
Table 2-18 shows the memory maps of all groups (for deï¬nitions see Table 2-2). Addresses 0x0000 to
0x0007 are only implemented in group G1 otherwise reserved.
Table 2-18. Block Memory Map (0x0000-0x027F)
Port
Global
Address
Register
(A)
0x0000 PORTAâPort A Data Register1
(B)
0x0001 PORTBâPort B Data Register1
0x0002 DDRAâPort A Data Direction Register1
0x0003 DDRBâPort B Data Direction Register1
(C)
0x0004 PORTCâPort C Data Register1
(D)
0x0005 PORTDâPort D Data Register1
0x0006 DDRCâPort C Data Direction Register1
0x0007 DDRDâPort D Data Direction Register1
E
0x0008 PORTEâPort E Data Register
0x0009
0x000A
:
0x000B
DDREâPort E Data Direction Register
Non-PIM address range2
(A) 0x000C PUCRâPull Control Register
(B)
(C)
0x000D Reserved
(D)
E
0x000E
:
0x001B
Non-PIM address range2
0x001C ECLKCTLâECLK Control Register
0x001D Reserved
0x001E IRQCRâIRQ Control Register
0x001F
0x0020
:
0x023F
Reserved
Non-PIM address range2
Access Reset Value
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
R/W
0x00
-
-
R/W
0x50
R
0x00
-
-
R/W
0xC0
R
0x00
R/W
0x00
R
0x00
-
-
Section/Page
2.4.3.1/2-205
2.4.3.2/2-205
2.4.3.3/2-206
2.4.3.4/2-207
2.4.3.5/2-207
2.4.3.6/2-208
2.4.3.7/2-209
2.4.3.8/2-209
-
2.4.3.11/2-211
-
2.4.3.12/2-213
2.4.3.13/2-213
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MC9S12G Family Reference Manual, Rev.1.23
186
Freescale Semiconductor
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