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S9S12G128F0MLH Datasheet, PDF (346/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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S12S Debug Module (S12SDBGV2)
If the comparator register contents coincide with the SWI/BDM vector address then an SWI in user code
could coincide with a DBG breakpoint. The CPU ensures that BDM requests have a higher priority than
SWI requests. Returning from the BDM/SWI service routine care must be taken to avoid a repeated
breakpoint at the same address.
Should a tagged or forced breakpoint coincide with a BGND in user code, then the instruction that follows
the BGND instruction is the ï¬rst instruction executed when normal program execution resumes.
NOTE
When program control returns from a tagged breakpoint using an RTI or
BDM GO command without program counter modiï¬cation it returns to the
instruction whose tag generated the breakpoint. To avoid a repeated
breakpoint at the same location reconï¬gure the DBG module in the SWI
routine, if conï¬gured for an SWI breakpoint, or over the BDM interface by
executing a TRACE command before the GO to increment the program ï¬ow
past the tagged instruction.
8.5 Application Information
8.5.1 State Machine scenarios
Deï¬ning the state control registers as SCR1,SCR2, SCR3 and M0,M1,M2 as matches on channels 0,1,2
respectively. SCR encoding supported by S12SDBGV1 are shown in black. SCR encoding supported only
in S12SDBGV2 are shown in red. For backwards compatibility the new scenarios use a 4th bit in each SCR
register. Thus the existing encoding for SCRx[2:0] is not changed.
8.5.2 Scenario 1
A trigger is generated if a given sequence of 3 code events is executed.
Figure 8-27. Scenario 1
SCR1=0011
SCR2=0010
State1
M1
State2
M2
SCR3=0111
State3
M0
Final State
Scenario 1 is possible with S12SDBGV1 SCR encoding
MC9S12G Family Reference Manual, Rev.1.23
348
Freescale Semiconductor
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