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S9S12G128F0MLH Datasheet, PDF (249/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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Port Integration Module (S12GPIMV1)
2.5.2.6 Wired-Or Mode Register (WOMx)
If the pin is used as an output this register turns off the active-high drive. This allows wired-or type
connections of outputs.
2.5.2.7 Interrupt Enable Register (PIEx)
If the pin is used as an interrupt input this register serves as a mask to the interrupt ï¬ag to enable/disable
the interrupt.
2.5.2.8 Interrupt Flag Register (PIFx)
If the pin is used as an interrupt input this register holds the interrupt ï¬ag after a valid pin event.
2.5.2.9 Pin Routing Register (PRRx)
This register allows software re-conï¬guration of the pinouts for speciï¬c peripherals in the 20 TSSOP
package only.
2.5.2.10 Package Code Register (PKGCR)
This register determines the package in use. Pre programmed by factory.
2.5.3 Pin Conï¬guration Summary
The following table summarizes the effect of the various conï¬guration bits, that is data direction (DDR),
output level (IO), pull enable (PE), pull select (PS) on the pin function and pull device 1.
The conï¬guration bit PS is used for two purposes:
1. Conï¬gure the sensitive interrupt edge (rising or falling), if interrupt is enabled.
2. Select either a pullup or pulldown device if PE is active.
1.
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
251
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