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S9S12G128F0MLH Datasheet, PDF (818/1292 Pages) Freescale Semiconductor, Inc – S12 CPU core, Up to 240 Kbyte on-chip flash with ECC | |||
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16 KByte Flash Module (S12FTMRG16K1V1)
Table 24-57. Set Field Margin Level Command Error Handling
Register
Error Bit
Error Condition
FSTAT
ACCERR
FPVIOL
Set if CCOBIX[2:0] != 001 at command launch
Set if command not available in current mode (see Table 24-25)
Set if an invalid FlashBlockSelectionCode[1:0] is supplied (See Table 24-32 )1
Set if an invalid margin level setting is supplied
None
MGSTAT1 None
MGSTAT0 None
1 As deï¬ned by the memory map for FTMRG32K1.
CAUTION
Field margin levels must only be used during verify of the initial factory
programming.
NOTE
Field margin levels can be used to check that Flash memory contents have
adequate margin for data retention at the normal level setting. If unexpected
results are encountered when checking Flash memory contents at ï¬eld
margin levels, the Flash memory contents should be erased and
reprogrammed.
24.4.6.14 Erase Verify EEPROM Section Command
The Erase Verify EEPROM Section command will verify that a section of code in the EEPROM is erased.
The Erase Verify EEPROM Section command deï¬nes the starting point of the data to be veriï¬ed and the
number of words.
Table 24-58. Erase Verify EEPROM Section Command FCCOB Requirements
CCOBIX[2:0]
FCCOB Parameters
Global address [17:16] to
000
0x10
identify the EEPROM
block
001
Global address [15:0] of the ï¬rst word to be veriï¬ed
010
Number of words to be veriï¬ed
Upon clearing CCIF to launch the Erase Verify EEPROM Section command, the Memory Controller will
verify the selected section of EEPROM memory is erased. The CCIF ï¬ag will set after the Erase Verify
EEPROM Section operation has completed. If the section is not erased, it means blank check failed, both
MGSTAT bits will be set.
MC9S12G Family Reference Manual, Rev.1.23
820
Freescale Semiconductor
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