MC68HC05K0 Datasheet, PDF (82/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Technical Data
Freescale Semiconductor, Inc.
8.5 COP Watchdog
Three counter stages at the end of the timer make up the mask optional
computer operating properly (COP) watchdog (see Figure 8-1). The
COP watchdog is a software error detection system that automatically
times out and resets the MCU if not cleared periodically by a program
sequence. Writing a logic 0 to bit 0 of the COP register, shown in
Figure 8-4, clears the COP watchdog and prevents a COP reset.
Address: $03F0
Bit 7
6
5
4
3
2
Read: 0
0
0
0
0
0
Write:
Reset: U
U
U
U
U
U
= Unimplemented
U = Unaffected
Figure 8-4. COP Register (COPR)
1
Bit 0
1
0
COPC
U
0
COPC — COP Clear Bit
This write-only bit resets the COP watchdog. Reading address $03F0
returns the ROM data at that address.
The COP watchdog is active in the run, wait, and halt modes of
operation. The STOP instruction disables the COP watchdog by clearing
the counter and turning off its clock source. In applications that depend
on the COP watchdog, the STOP instruction can be disabled (converted
to halt) by a mask option.
In applications that have wait cycles longer than the COP timeout period,
the COP watchdog can be disabled by a mask option.
NOTE:
If the voltage on the IRQ/V_PP pin exceeds a nominal 1.5 × V_DD, the COP
watchdog turns off and remains off until the IRQ/V_PP voltage falls below
2 × V_DD.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Multifunction Timer
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