MC68HC05K0 Datasheet, PDF (71/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port B
data register returns the logic state of the pin. Reset has no effect on port
B data.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
PB1
PB0
Write:
Reset:
Unaffected by reset
Alternate
Function:
OSC3
= Unimplemented
Figure 7-5. Port B Data Register (PORTB)
PB1/OSC3 — Port B Data Bit 1
This read/write bit is software programmable. Data direction of PB1 is
under the control of the DDRB1 bit in data direction register B.
When the 3-pin RC oscillator mask option is selected, PB1/OSC3 is
used as an oscillator output. Using the 3-pin RC oscillator
configuration affects port B in these ways:
• Bit PB1 can be used as a read/write storage location without
affecting the oscillator. Reset has no effect on bit PB1.
• Bit DDRB1 in data direction register B can be used as a read/write
storage location without affecting the oscillator. Reset clears
DDRB1.
• The PB1/OSC3 pulldown device is disabled.
PB0 — Port B Data Bit 0
This read/write bit is software-programmable. Data direction of PB0 is
under the control of the DDRB0 bit in data direction register B.
Bits 7–2 — Not used
Bits 7–2 always read as logic 0s.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Technical Data