MC68HC05K0 Datasheet, PDF (69/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port A
7.3.4 Port A External Interrupts
If the mask option for port A external interrupts is selected, the PA3–PA0
pins serve as external interrupt pins in addition to the IRQ/V_PP pin.
External interrupts can be positive edge-triggered or positive edge- and
high level-triggered.
NOTE:
When testing for external interrupts, the BIH and BIL instructions test the
voltage on the IRQ/V_PP pin, not the state of the internal IRQ signal.
Therefore, BIH and BIL do not test the port A external interrupt pins.
Port A interrupts are not sensitive to the direction of the port pins. Driving
a logic 1 on PA0–PA3 while port interrupts are enabled will cause an
interrupt, even if PA0–PA3 are set to outputs.
7.3.5 Port A Logic
Figure 7-4 shows the port A I/O logic.
READ $0004
WRITE $0004
WRITE $0000
DATA DIRECTION
REGISTER A
BIT DDRAx
PORT A DATA
REGISTER
BIT PAx
READ $0000
WRITE $0010
PULLDOWN
REGISTER A
BIT PDIAx
RESET
PULLDOWNS ENABLED (ACTIVE LOW)
(MASK OPTION)
Figure 7-4. Port A I/O Circuit
EXTERNAL
INTERRUPT
REQUEST
(PINS PA3–PA0)
PAx
8-mA SINK
CAPABILITY
(PINS PA7–PA4)
100-mA
PULLDOWN
DEVICE
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Parallel Input/Output (I/O)
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Technical Data