MC68HC05K0 Datasheet, PDF (107/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Instruction Set
Instruction Set Summary
Source
Form
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
LDX #opr
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
MUL
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
NOP
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
Table 10-6. Instruction Set Summary (Sheet 4 of 6)
Operation
Jump to Subroutine
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Logical Shift Left (Same as ASL)
Logical Shift Right
Unsigned Multiply
Negate Byte (Two’s Complement)
No Operation
Logical OR Accumulator with Memory
Rotate Byte Left through Carry Bit
Description
Effect
on CCR
H I NZC
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Effective Address
—————
DIR
EXT
IX2
IX1
IX
BD dd 5
CD hh ll 6
DD ee ff 7
ED ff 6
FD
5
A ← (M)
—— ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
A6 ii 2
B6 dd 3
C6 hh ll 4
D6 ee ff 5
E6 ff 4
F6
3
X ← (M)
—— ↕ ↕ —
IMM
DIR
EXT
IX2
IX1
IX
AE ii 2
BE dd 3
CE hh ll 4
DE ee ff 5
EE ff 4
FE
3
C
b7
0
b0
DIR 38 ^dd 5
INH 48
3
— — ↕ ↕ ↕ INH 58
3
IX1 68 ff 6
IX 78
5
0
b7
C
b0
DIR 34 ^dd 5
INH 44
3
— — 0 ↕ ↕ INH 54
3
IX1 64 ff 6
IX 74
5
X : A ← (X) × (A)
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
0 — — — 0 INH 42
1
1
DIR 30 ^dd 5
INH 40
3
— — ↕ ↕ ↕ INH 50
3
IX1 60 ff 6
IX 70
5
A ← (A) ∨ (M)
C
b7
b0
—————
—— ↕ ↕ —
—— ↕ ↕ ↕
INH
IMM
DIR
EXT
IX2
IX1
IX
DIR
INH
INH
IX1
IX
9D
2
AA ii 2
BA dd 3
CA hh ll 4
DA ee ff 5
EA ff 4
FA
3
39 ^dd 5
49
3
59
3
69 ff 6
79
5
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Instruction Set
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Technical Data