MC68HC05K0 Datasheet, PDF (80/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Technical Data
Freescale Semiconductor, Inc.
RTIFR — Real-Time Interrupt Flag Reset Bit
Writing a logic 1 to this write-only bit clears the RTIF bit. RTIFR
always reads as a logic 0. Reset does not affect RTIFR.
RT1 and RT0 — Real-Time Interrupt Select Bits 1 and 0
These read/write bits select 1of four real-time interrupt rates, as
shown in Table 8-1. Because the selected RTI output drives the COP
watchdog, changing the real-time interrupt rate also changes the
counting rate of the COP watchdog. Reset sets RT1 and RT0,
selecting the longest COP timeout period and real-time interrupt
period.
Table 8-1. Real-Time Interrupt Rate Selection
RT1:RT0
Number
of Cycles
to RTI
RTI
Period⁽¹⁾
00
2¹⁴ = 16,384
8.2 ms
01
2¹⁵ = 32,768
16.4 ms
10
2¹⁶ = 65,536
32.8 ms
11
2¹⁷ = 131,072 ^{65.5 ms}
1. At 2-MHz bus, 4-MHz XTAL, 0.5 µs per cycle
Number
of Cycles
to COP Reset
2¹⁷ = 131,072
2¹⁸ = 262,144
2¹⁹ = 524,288
2²⁰ = 1,048,576
COP Timeout
Period⁽¹⁾
65.5 ms
131.1 ms
262.1 ms
524.3 ms
NOTE:
Be careful when altering RT0 or RT1 when a timeout is imminent or
uncertain. If the selected RTx is modified during a cycle when the
counter is switching, an RTIF can be missed or an additional RTIF can
be generated. To avoid this problem, clear the COP just before changing
RT1 and RT0.
The COP timer is the RTI timer divided by eight. However, clearing the
COP clears only the last three dividers. It does not clear the RTI section
of the divider chain. Therefore, the COP timeout period is in the range of
seven to eight times the RTI period.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Multifunction Timer
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