MC68HC05K0 Datasheet, PDF (54/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Technical Data
Freescale Semiconductor, Inc.
5.3 Reset Types
A reset immediately stops the operation of the instruction being
executed, initializes certain control bits, and loads the program counter
with a user-defined reset vector address.
These conditions produce a reset:
• Initial power-up (power-on reset)
• A logic 0 applied to the RESET pin (external reset)
• Timeout of the mask-optional computer operating properly (COP)
watchdog (COP reset)
• An opcode fetch from an address not in the read-only memory
(ROM) or random-access memory (RAM) (illegal address reset)
• V_DD voltage below LVR trip point (mask-optional low-voltage
reset)
Figure 5-1 is a block diagram of the reset sources.
5.3.1 Power-On Reset
A positive transition on the V_DD pin generates a power-on reset. The
power-on reset is strictly for power-up conditions and cannot be used to
detect drops in power supply voltage.
A 4064 t_cyc (internal clock cycle) delay after the oscillator becomes
active allows the clock generator to stabilize. If the RESET pin is at a
logic 0 at the end of 4064 t_cyc, the MCU remains in the reset condition
until the signal on the RESET pin goes to a logic 1.
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Resets
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