MC68HC05K0 Datasheet, PDF (45/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Freescale Semiconductor, Inc.
Interrupts
Interrupt Types
4.3.2.1 IRQ/V_PP Pin
An interrupt signal on the IRQ/V_PP pin latches an external interrupt
request. The IRQ/V_PP pin contains an internal Schmitt trigger as part of
its input to improve noise immunity. After completing the current
instruction, the CPU tests these bits:
• IRQF bit in the interrupt status and control register
• IRQE bit in the interrupt status and control register
• I bit in the condition code register
If both the IRQF bit and the IRQE bit are set, and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQF bit
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request. Figure 4-1 shows the logic for
external interrupts.
The IRQ/V_PP pin is negative-edge triggered only or negative-edge and
low-level triggered, depending on the mask option selected.
When the edge- and level-sensitive trigger mask option is selected:
• A falling edge or a low level on the IRQ/V_PP pin latches an external
interrupt request.
• As long as the IRQ/V_PP pin is low, an external interrupt request is
present, and the CPU continues to execute the interrupt service
routine. The edge- and level-sensitive trigger option allows
connection to the IRQ/V_PP pin to multiple wired-OR interrupt
sources.
When the edge-sensitive only trigger mask option is selected:
• A falling edge of the IRQ/V_PP pin latches an external interrupt
request.
• A subsequent interrupt request can be latched only after the
voltage level on the IRQ/V_PP pin returns to logic 1 and then falls
again to logic 0.
NOTE: If the IRQ/V_PP pin is not in use, connect it to the V_DD pin.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Interrupts
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Technical Data