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MC68HC05K0 Datasheet, PDF (47/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit
Freescale Semiconductor, Inc.
Interrupts
Interrupt Types
the I bit is cleared during the return from interrupt, the CPU can
recognize the new interrupt request.
The PA3–PA0 pins are positive edge triggered only or positive-edge and
high- level triggered, depending on the mask option selected.
When the positive edge and high level-sensitive trigger mask option is
selected:
• A rising edge or a high level on a PA3–PA0 pin latches an external
interrupt request if and only if all other PA3–PA0 pins are low and
the IRQ/VPP pin is high.
• A falling edge or a low level on the IRQ/VPP pin latches an external
interrupt request if and only if all of the PA3–PA0 pins are low.
• As long as any PA3–PA0 pin is high or the IRQ/VPP pin is low, an
external interrupt request is present, and the CPU continues to
execute the interrupt service routine.
Edge- and level-sensitive triggering allows multiple external interrupt
sources to be wire-ORed to any of the PA3–PA0 pins. As long as any
source is holding a PA3–PA0 pin high, an external interrupt request is
latched, and the CPU continues to execute the interrupt service routine.
When the positive edge-sensitive-only trigger mask option is selected:
• A rising edge on any one of the PA3–PA0 pins latches an external
interrupt request if all other PA3–PA0 pins are low and the
IRQ/VPP pin is high.
• A falling edge on the IRQ/VPP pin latches an external interrupt
request if and only if all of the PA3–PA0 pins are low.
• A subsequent PA3–PA0 pin interrupt request can be latched only
after the voltage level of the previous PA3–PA0 interrupt signal
returns to a logic 0 and then rises again to a logic 1.
• A subsequent IRQ/VPP pin interrupt request can be latched only
after the voltage level of the previous IRQ/VPP interrupt signal
returns to a logic 1 and then falls again to a logic 0.
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Interrupts
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Technical Data