MC68HC05K0 Datasheet, PDF (50/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Technical Data
Freescale Semiconductor, Inc.
4.4 Interrupt Processing
To begin servicing an interrupt, the CPU:
• Stores the CPU registers on the stack in the order shown in
Figure 4-3
• Sets the I bit in the condition code register to prevent further
interrupts
• Loads the program counter with the contents of the appropriate
interrupt vector locations:
– $03FC and $03FD (software interrupt vector)
– $03FA and $03FB (external interrupt vector)
– $03F8 and $03F9 (timer interrupt vector)
The return-from-interrupt (RTI) instruction causes the CPU to recover
the CPU registers from the stack as shown in Figure 4-3.
$00E0 (BOTTOM OF STACK)
$00E1
$00E2
•
•
UNSTACKING
ORDER
•
•
•
•
5
1
4
2
3
3
2
4
1
5
STACKING
ORDER
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PROGRAM COUNTER (HIGH BYTE)
PROGRAM COUNTER (LOW BYTE)
•
•
•
•
•
•
$00FD
$00FE
$00FF (TOP OF STACK)
Figure 4-3. Interrupt Stacking Order
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Interrupts
For More Information On This Product,
Go to: www.freescale.com