MC68HC05K0 Datasheet, PDF (46/154 Pages) Freescale Semiconductor, Inc – HCMOS Microcontroller Unit

Technical Data
Freescale Semiconductor, Inc.
TO BIH & BIL
IRQ
INSTRUCTION
PROCESSING
LEVEL-SENSITIVE TRIGGER
PA3
(MASK OPTION)
V_DD
PA2
IRQ
LATCH
EXTERNAL
R
INTERRUPT
REQUEST
PA1
PA0
PORT A
EXTERNAL INTERRUPTS
ENABLED
(MASK OPTION)
RST
IRQ VECTOR FETCH
IRQ STATUS AND CONTROL REGISTER
INTERNAL DATA BUS
Figure 4-1. External Interrupt Logic
4.3.2.2 PA3–PA0 Pins
The mask option for port A external interrupts enables pins PA3–PA0 to
serve as additional external interrupt sources. The PA3–PA0 pins do not
contain internal Schmitt triggers. An interrupt signal on one of the
PA3–PA0 pins latches an external interrupt request. After completing
the current instruction, the CPU tests these bits:
• IRQF bit (IRQ latch)
• IRQE bit in the interrupt status and control register
• I bit in the condition code register
If both the IRQ latch and the IRQE bit are set and the I bit is clear, the
CPU then begins the interrupt sequence. The CPU clears the IRQ latch
while it fetches the interrupt vector, so that another external interrupt
request can be latched during the interrupt service routine. As soon as
Technical Data
MC68HC05K0 • MC68HC05K1 — Rev. 2.0
Interrupts
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