MC9328MX21_10 Datasheet, PDF (64/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
Table 43. EIM Bus Timing Parameters
Ref No.
Parameter
1.8 V ± 0.1 V 3.0 V ± 0.3 V
1.8 V ±
0.1 V _Unit
Min Typical Max Min Typical Max
1a Clock fall to address valid
3.97 6.02 9.89 3.83 5.89
9.79
ns
1b Clock fall to address invalid
3.93 6.00 9.86 3.81 5.86
9.76
ns
2a Clock fall to chip-select valid
3.47 5.59 8.62 3.30 5.09
8.45
ns
2b Clock fall to chip-select invalid
3.39 5.09 8.27 3.15 4.85
8.03
ns
3a Clock fall to Read (Write) Valid
3.51 5.56 8.79 3.39 5.39
8.51
ns
3b Clock fall to Read (Write) Invalid
4a
Clock¹ rise to Output Enable Valid
4b
Clock¹ rise to Output Enable Invalid
4c
Clock¹ fall to Output Enable Valid
4d
Clock¹ fall to Output Enable Invalid
5a
Clock¹ rise to Enable Bytes Valid
5b
Clock¹ rise to Enable Bytes Invalid
5c
Clock¹ fall to Enable Bytes Valid
5d
Clock¹ fall to Enable Bytes Invalid
6a
Clock¹ fall to Load Burst Address Valid
6b
Clock¹ fall to Load Burst Address Invalid
6c
Clock¹ rise to Load Burst Address Invalid
7a
Clock¹ rise to Burst Clock rise
7b
Clock¹rise to Burst Clock fall
7c
Clock¹ fall to Burst Clock rise
7d
Clock¹ fall to Burst Clock fall
3.59 5.37 9.14 3.36 5.20
8.50
ns
3.62 5.49 8.98 3.46 5.33
9.02
ns
3.70 5.61 9.26 3.46 5.37
8.81
ns
3.60 5.48 8.77 3.44 5.30
8.88
ns
3.69 5.62 9.12 3.42 5.36
8.60
ns
3.69 5.46 8.71 3.46 5.25
8.54
ns
4.64 5.47 8.70 3.46 5.25
8.54
ns
3.52 5.06 8.39 3.41 5.18
8.36
ns
3.50 5.05 8.27 3.41 5.18
8.36
ns
3.65 5.28 8.69 3.30 5.23
8.81
ns
3.65 5.67 9.36 3.41 5.43
9.13
ns
3.66 5.69 9.48 3.33 5.47
9.25
ns
3.50 5.22 8.42 3.26 4.99
8.19
ns
3.49 5.19 8.30 3.31 5.03
8.17
ns
3.50 5.22 8.39 3.26 4.98
8.15
ns
3.49 5.19 8.29 3.31 5.02
8.12
ns
8a Read Data setup time
4.54
–
– 4.54
–
–
ns
8b Read Data hold time
9a
Clock¹ rise to Write Data Valid
9b
Clock¹ fall to Write Data Invalid
9c
Clock¹ rise to Write Data Invalid
0.5
–
–
0.5
–
–
ns
4.13 5.86 9.16 3.95 6.36 10.31 ns
4.10 5.79 9.15 4.04 6.27
9.16
ns
4.02 5.81 9.37 4.22 5.29
9.24
ns
10a DTACK setup time
2.65 4.63 8.40 2.64 4.61
8.41
ns
11 Burst Clock (BCLK) cycle time
15
–
–
15
–
–
ns
1. Clock refers to the system clock signal, HCLK, generated from the System DPLL
MC9328MX21 Technical Data, Rev. 3.4
64
Freescale Semiconductor