MC9328MX21_10 Datasheet, PDF (50/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
Table 33. SDRAM Refresh Timing Parameters
Ref
No.
Parameter
1.8 V ± 0.1 V
Minimum Maximum
3.0 V ± 0.3 V
Minimum Maximum
1 SDRAM clock high-level width
3.00
–
3
–
2 SDRAM clock low-level width
3.00
–
3
–
3 SDRAM clock cycle time
7.5
–
7.5
–
4 Address setup time
3.67
–
2
–
5 Address hold time
2.95
–
2
–
6 Precharge cycle period
t_RP1
–
t_RP1
–
7 Auto precharge command period
t_RC1
–
t_RC1
–
1. t_RP and t_RC = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
Unit
ns
ns
ns
ns
ns
ns
ns
SDCLK
CS
RAS
CAS
WE
ADDR
DQ
DQM
CKE
BA
Figure 41. SDRAM Self-Refresh Cycle Timing Diagram
MC9328MX21 Technical Data, Rev. 3.4
50
Freescale Semiconductor