MC9328MX21_10 Datasheet, PDF (36/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
3.12 Multimedia Card/Secure Digital Host Controller
The DMA interface block controls all data routing between the external data bus (DMA access), internal
MMC/SD module data bus, and internal system FIFO access through a dedicated state machine that
monitors the status of FIFO content (empty or full), FIFO address, and byte/block counters for the MMC/
SD module (inner system) and the application (user programming).
3a
12
3b
4b
Bus Clock
4a
5a
5b
CMD_DAT Input
Valid Data
Valid Data
CMD_DAT Output
7
Valid Data
Valid Data
6a
6b
Figure 25. Chip-Select Read Cycle Timing Diagram
Table 26. SDHC Bus Timing Parameters
Ref
No.
Parameter
1 CLK frequency at Data transfer Mode (PP)¹â€”10/30 cards
2 CLK frequency at Identification Mode²
3a Clock high time¹â€”10/30 cards
3b Clock low time¹â€”10/30 cards
4a Clock fall time¹â€”10/30 cards
4b Clock rise time¹â€”10/30 cards
5a Input hold time³â€”10/30 cards
5b Input setup time³â€”10/30 cards
6a Output hold time³â€”10/30 cards
6b Output setup time³â€”10/30 cards
7 Output delay time³
1. C_L ≤ 100 pF / 250 pF (10/30 cards)
2. C_L ≤ 250 pF (21 cards)
3. C_L ≤ 25 pF (1 card)
1.8 V ± 0.1 V
Min
0
0
6/33
15/75
–
–
5.7/5.7
5.7/5.7
5.7/5.7
5.7/5.7
0
Max
25/5
400
–
–
10/50 (5.00)³
14/67 (6.67)³
–
–
–
–
16
3.0 V ± 0.3 V
Min
0
0
10/50
10/50
–
–
5/5
5/5
5/5
5/5
0
Max
25/5
400
–
–
10/50
10/50
–
–
–
–
14
Unit
MHz
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
MC9328MX21 Technical Data, Rev. 3.4
36
Freescale Semiconductor