MC9328MX21_10 Datasheet, PDF (43/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

3.13 External Memory Interface (EMI) Electricals
Specifications
3.13.1 NAND-Flash Controller (NFC) Interface
Figure 33, Figure 34, Figure 35, and Figure 36 depict the relative timing requirements among different
signals of the NFC at module level, and Table 29 lists the timing parameters. The NAND Flash Controller
(NFC) timing parameters are based on the internal NFC clock generated by the Clock Controller module,
where time T is the period of the NFC clock in ns. Per the i.MX21 Reference Manual, specifically the
Phase-Locked (PLL), Clock, and Reset Controller chapter, the NFC clock is derived from the same clock
which drives the CPU clock (FCLK) that is fed through the NFCDIV block to generate the NFC clock.
The relationship between the NFC clock and the external timing parameters of the NFC is provided in
Table 29.
Table 29 also provides two examples of external timing parameters with NFC clock frequencies of
22.17 MHz and 33.25 MHz. For example, assuming a 266 MHz FCLK (CPU clock), NFCDIV should be
set to divide-by-12 to generate a 22.17 MHz NFC clock and divide-by-8 to generate a 33.25 MHz NFC
clock. The user should compare the parameters of the selected NAND Flash memory with the NFC
external timing parameters to determine the proper NFC clock. The maximum NFC clock allowed is
66 MHz. It should also be noted that the default NFC clock on power up is 16.63 MHz.
NFCLE
NF1
NF3
NFCE
NF5
NFWE
NF6
NFALE
NF2
NF4
NF7
NFIO[7:0]
NF8
NF9
command
Figure 33. Command Latch Cycle Timing DIagram
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
43