MC9328MX21_10 Datasheet, PDF (30/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
Table 19. Timing Parameters for Figure 14 through Figure 18
Ref No.
Parameter
Minimum
Maximum Unit
1 SPI_RDY to SS output low
2 SS output low to first SCLK edge
2T ¹
3·Tsclk ²
–
ns
–
ns
3 Last SCLK edge to SS output high
2·Tsclk
–
ns
4 SS output high to SPI_RDY low
0
–
ns
5 SS output pulse width
Tsclk + WAIT ³
–
ns
6 SS input low to first SCLK edge
T
–
ns
7 SS input pulse width
T
–
ns
1. T = CSPI system clock period (PERCLK2).
2. Tsclk = Period of SCLK.
3. WAIT = Number of bit clocks (SCLK) or 32.768 kHz clocks per Sample Period Control
Register.
3.10 LCD Controller
This section includes timing diagrams for the LCD controller. For detailed timing diagrams of the LCD
controller with various display configurations, refer to the LCD controller chapter of the i.MX21 Reference
Manual.
T1
LSCLK
LD[17:0]
T2
T3
Figure 19. SCLK to LD Timing Diagram
Table 20. LCDC SCLK Timing Parameters
Symbol
Parameter
3.0 ± 0.3V
Minimum
Maximum
T1
SCLK period
23
2000
T2
Pixel data setup time
11
–
T3
Pixel data up time
11
–
The pixel clock is equal to LCDC_CLK / (PCD + 1).
When it is in CSTN, TFT or monochrome mode with bus width = 1, SCLK is equal to the pixel clock.
When it is in monochrome with other bus width settings, SCLK is equal to the pixel clock divided by bus width.
The polarity of SCLK and LD can also be programmed.
Maximum frequency of SCLK is HCLK / 3 for TFT and CSTN, otherwise LD output will be incorrect.
Unit
ns
ns
ns
MC9328MX21 Technical Data, Rev. 3.4
30
Freescale Semiconductor