MC9328MX21_10 Datasheet, PDF (22/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
1T
BMI_CLK/CS
BMI_READ_REQ
BMI_D[15:0]
Tdh
Tds
TxD1 TxD2
Trh
Last TxD
BMI_WRITE
Ts
Figure 6. MMD (ATI) Drives Clock, MMD Read BMI Timing
(MMD_MODE_SEL=1, MASTER_MODE_SEL=0,MMD_CLKOUT=0)
Table 14. MMD Read BMI Timing Table when MMD Drives Clock
Item
Clock period
write setup time
read_req hold time
transfer data setup time
transfer data hold time
Symbol
Minimum
Typical
Maximum
Unit
1T
33.3
–
Ts
11
–
Trh
6
–
Tds
6
–
Tdh
6
-
–
ns
–
ns
24
ns
14
ns
14
ns
Note: All the timings assume that the hclk is running at 133 MHz.
Note: The MIN period of the 1T is assumed that MMD latch data at falling edge.
Note: If the MMD latch data at next rising edge, the ideally max clock can be as much as double, but because the BMI data pads
are slow pads and it max frequency can only up to 18MHz, the max clock frequency can only up to 36 MHz.
3.8.1.1.2 MMD Write BMI Timing
Figure 7 shows the MMD write BMI timing when MMD drives clock. On each falling edge of BMI_CLK/
CS BMI checks the BMI_WRITE logic level to determine if the current cycle is a write cycle. If the BMI_
WRITE is logic low, it latches data into the RxFIFO on each falling edge of BMI_CLK/CS signal.
MC9328MX21 Technical Data, Rev. 3.4
22
Freescale Semiconductor