MC9328MX21_10 Datasheet, PDF (20/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
The output External Grant signal from the DMAC is an active-low signal.When the following conditions
are true, the External DMA Grant signal is asserted with the initiation of the DMA burst.
• The DMA channel for which the DMA burst is ongoing has request source as external DMA
Request
(as per source select register setting).
• REN and CEN bit of this channel are set.
• External DMA Request is asserted.
After the grant is asserted, the External DMA request will not be sampled until completion of the DMA
burst. As the external request is synchronized, the request synchronization will not be done during this
period. The priority of the external request becomes low for the next consecutive burst, if another DMA
request signal is asserted.
Worst case—that is, the smallest burst (1 byte read/write) timing diagrams are shown in Figure 4 and
Figure 5. Minimum and maximum timings for the External request and External grant signals are present
in Table 13.
Figure 4 shows the minimum time for which the External Grant signal remains asserted when an External
DMA request is de-asserted immediately after sensing grant signal active.
Ext_DMAReq
Ext_DMAGrant
t_{min_assert}
Figure 4. Assertion of DMA External Grant Signal
Figure 5 shows the safe maximum time for which External DMA request can be kept asserted, after
sensing grant signal active such that a new burst is not initiated.
Ext_DMAReq
Ext_DMAGrant
t_{max_req_assert}
Data read from
External device
t_{max_read}
Data written to
External device
t_{max_write}
NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
Figure 5. Safe Maximum Timings for External Request De-Assertion
MC9328MX21 Technical Data, Rev. 3.4
20
Freescale Semiconductor