MC9328MX21_10 Datasheet, PDF (37/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
3.12.1 Command Response Timing on MMC/SD Bus
The card identification and card operation conditions timing are processed in open-drain mode. The card
response to the host command starts after exactly N_ID clock cycles. For the card address assignment,
SET_RCA is also processed in the open-drain mode. The minimum delay between the host command and
card response is NCR clock cycles as illustrated in Figure 26. The symbols for Figure 26 through
Figure 30 are defined in Table 27.
Table 27. State Signal Parameters for Figure 26 through Figure 30
Card Active
Host Active
Symbol
Z
D
Definition
High impedance state
Data bits
Symbol
S
T
*
Repetition
P
CRC Cyclic redundancy check bits (7 bits)
E
Definition
Start bit (0)
Transmitter bit
(Host = 1, Card = 0)
One-cycle pull-up (1)
End bit (1)
Host Command
CMD S T Content CRC E Z
N_ID cycles
CID/OCR
******
Z S T Content Z Z Z
Identification Timing
Host Command
N_CR cycles
CID/OCR
CMD S T Content CRC E Z ******
Z S T Content Z Z Z
SET_RCA Timing
Figure 26. Timing Diagrams at Identification Mode
After a card receives its RCA, it switches to data transfer mode. As shown on the first diagram in
Figure 27, SD_CMD lines in this mode are driven with push-pull drivers. The command is followed by a
period of two Z bits (allowing time for direction switching on the bus) and then by P bits pushed up by the
responding card. The other two diagrams show the separating periods N_RC and N_CC.
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
37