MC9328MX21_10 Datasheet, PDF (13/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Signal Name
SYS_CLK1
SSI2_CLK
SSI2_TXD
SSI2_RXD
SSI2_FS
SYS_CLK2
SSI3_CLK
SSI3_TXD
SSI3_RXD
SSI3_FS
SAP_CLK
SAP_TXD
SAP_RXD
SAP_FS
I2C_CLK
I2C_DATA
OWIRE
PWMO
PF[16]
KP_COL[7:0]
KP_ROW[7:0]
NVDD
NVSS
Signal Descriptions
Table 2. i.MX21 Signal Descriptions (Continued)
Function/Notes
SSI1 master clock. Multiplexed with TOUT.
Serial clock signal which is output in master or input in slave.
Transmit serial data signal
Receive serial data
Frame Sync signal which is output in master and input in slave.
SSI2 master clock. Multiplexed with TOUT.
Serial clock signal which is output in master or input in slave. Multiplexed with SLCDC2_CLK
Transmit serial data signal which is multiplexed with SLCDC2_CS
Receive serial data which is multiplexed with SLCDC2_RS
Frame Sync signal which is output in master and input in slave. Multiplexed with SLCDC2_D0.
Serial clock signal which is output in master or input in slave.
Transmit serial data
Receive serial data
Frame Sync signal which is output in master and input in slave.
I²C
I²C Clock
I²C Data
1-Wire
1-Wire input and output signal. This signal is multiplexed with JTAG RTCK.
PWM
PWM Output. This signal is multiplexed with PC_SPKOUT of PCMCIA, as well as TOUT2 and TOUT3
of the General Purpose Timer module.
General Purpose Input/Output
Dedicated GPIO. When unused, program this signal as an input with the on-chip pull-up resistor
enabled.
Keypad
Keypad Column selection signals. KP_COL[7:6] are multiplexed with UART2_CTS and UART2_TXD
respectively. Alternatively, KP_COL6 is also available on the internal factory test signal TEST_WB2. The
Function Multiplexing Control Register in the System Control chapter must be used in conjunction with
programming the GPIO multiplexing (to select the alternate signal multiplexing) to choose which signal
KP_COL6 is available.
Keypad Row selection signals. KP_ROW[7:6] are multiplexed with UART2_RTS and UART2_RXD
signals respectively. Alternatively, KP_ROW7 and KP_ROW6 are available on the internal factory test
signals TEST_WB0 and TEST_WB1 respectively. The Function Multiplexing Control Register in the
System Control chapter must be used in conjunction with programming the GPIO multiplexing (to select
the alternate signal multiplexing) to choose which signals KP_ROW6 and KP_ROW7 are available.
Noisy Supply Pins
Noisy Supply for the I/O pins. There are six (6) I/O voltages, NVDD1 through NVDD6.
Noisy Ground for the I/O pins
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
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