MC9328MX21_10 Datasheet, PDF (47/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
3.15 SDRAM Memory Controller
The following figures (Figure 38 through Figure 41) and their associated tables specify the timings related
to the SDRAMC module in the i.MX21.
1
SDCLK
CS
2
3S
3
RAS
CAS
WE
3S
3H
3S
3H
3H
3S
3H
ADDR
DQ
DQM
4S 4H
ROW/BA
COL/BA
8
5
3S
6
Data
7
3H _{Note: CKE is high during the read/write cycle.}
Figure 38. SDRAM Read Cycle Timing Diagram
Table 31. SDRAM Read Cycle Timing Parameter
Ref
No.
Parameter
1 SDRAM clock high-level width
2 SDRAM clock low-level width
3 SDRAM clock cycle time
3S CS, RAS, CAS, WE, DQM setup time
3H CS, RAS, CAS, WE, DQM hold time
1.8 V ± 0.1 V
Minimum Maximum
3.0 V ± 0.3 V
Minimum Maximum
Unit
3.00
–
3
–
ns
3.00
–
3
–
ns
7.5
–
7.5
–
ns
4.78
–
3
–
ns
3.03
–
2
–
ns
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
47