MC9328MX21_10 Datasheet, PDF (29/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

Specifications
becomes an input signal, and is used to latch data into or load data out to the internal data shift registers,
as well as to increment the data FIFO.
SS
1
SPIRDY
2
3
5
4
SCLK, MOSI, MISO
Figure 14. Master CSPI Timing Diagram Using SPI_RDY Edge Trigger
SS
SPIRDY
SCLK, MOSI, MISO
Figure 15. Master CSPI Timing Diagram Using SPI_RDY Level Trigger
SS (output)
SCLK, MOSI, MISO
Figure 16. Master CSPI Timing Diagram Ignore SPI_RDY Level Trigger
SS (input)
SCLK, MOSI, MISO
Figure 17. Slave CSPI Timing Diagram FIFO Advanced by BIT COUNT
SS (input)
6
7
SCLK, MOSI, MISO
Figure 18. Slave CSPI Timing Diagram FIFO Advanced by SS Rising Edge
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
29