MC9328MX21_10 Datasheet, PDF (19/100 Pages) Freescale Semiconductor, Inc – 266 MHz i.MX family of microprocessors

5
RESET_IN
HRESET
RESET_OUT
6
Specifications
14 cycles @ CLK32
4
CLK32
HCLK
Figure 3. Timing Relationship with RESET_IN
Table 12. Reset Module Timing Parameters
Ref
No.
Parameter
1 Width of input POWER_ON_RESET
2 Width of internal POWER_ON_RESET
(CLK32 at 32 kHz)
3 7k to 32k-cycle stretcher for SDRAM reset
4 14k to 32k-cycle stretcher for internal system reset HRESERT
and output reset at pin RESET_OUT
5 Width of external hard-reset RESET_IN
6 4k to 32k-cycle qualifier
1.8 V ± 0.10 V 3.0 V ± 0.30 V
Unit
Min Max Min Max
800 – 800 –
ms
300 300 300 300
ms
7
7
7
7 Cycles of CLK32
14 14 14 14 Cycles of CLK32
4
–
4
– Cycles of CLK32
4
4
4
4 Cycles of CLK32
3.7 External DMA Request and Grant
The External DMA request is an active low signal to be used by devices external to i.MX21 processor to
request the DMAC for data transfer.
After assertion of External DMA request the DMA burst will start when the channel on which the External
request is the source (as per the RSSR settings) becomes the current highest priority channel. The external
device using the External DMA request should keep its request asserted until it is serviced by the DMAC.
One External DMA request will initiate one DMA burst.
MC9328MX21 Technical Data, Rev. 3.4
Freescale Semiconductor
19